MTA4ATF51264HZ-3G2R1

MTA4ATF51264HZ-3G2R1 is a high-speed DDR4 SDRAM module that uses a DDR4 SDRAM device with two or four internal memory bank groups. DDR4 SDRAM module utilize 4- and 8-bit-wide DDR4 SDRAM devices have four internal bank groups consisting of four memory banks each, providing a total of 16 banks. 16-bit-wide DDR4 SDRAM device has two internal bank groups consisting of four memory banks each, providing a total of eight banks. DDR4 SDRAM module benefits from the DDR4 SDRAM's use of an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single READ or WRITE operation for the DDR4 SDRAM effectively consists of a single 8n-bit-wide, four-clock data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. DDR4 module uses two sets of differential signals: DQS_t and DQS_c to capture data and CK_t and CK_c to capture commands, addresses, and control signals.

• 4GB module density, 512 Meg x 64 configuration, 25.6GB/s module bandwidth
• 0.62ns/3200MT/s memory clock/data rate, 22-22-22 clock cycles (CL-tRCD-tRP)
• Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
• Low-power auto self refresh, data bus inversion for data bus, terminated control command/addr bus
• On-die VREFDQ generation and calibration, single-rank, fly-by topology
• On-board I²C serial presence-detect (SPD) EEPROM, 8 internal banks; 2 groups of 4 banks each
• Fixed burst chop of 4 and burst length of 8 via the mode register set (MRS), gold edge contacts
• 260-pin DIMM package
• Commercial operating temperature range from 0°C ≤ TOPER ≤ 95°C